A problem known as impact ionization occurs in MOS semiconductor devices which problem produces a non-linearity when the devices are used as gain stages. The problem occurs when electric fields in the devices become so large that free electrons traveling through the devices gain enough energy in the field to strip additional electrons from the molecular lattice. Consequently, the problem has become more severe as device sizes have been reduced and/or supply voltages increased.
For example, in a conventional n-channel MOS transistor in a 3 micron, 10 volt, CMOS process, the electric field strength at the drain end of the channel becomes high enough to cause impact ionization when the drain-source voltage increases above approximately five volts. The magnitude of the peak field strength is a function of a number of variables and cannot easily be controlled to reduce the effect of impact ionization. The effect is also present in p-channel devices, although it occurs at higher supply voltages.
Free electrons which are stripped from the lattice eventually migrate to either the source electrode or the substrate (backgate electrode), thereby creating an undesirable current. This current affects the electrical characteristics of the device. More particularly, in a typical MOS device, as the drain-source voltage increases from zero volts, the device enters a linear region in which the drain current increases approximately proportional to the drain-source voltage. As the drain-source voltage is increased further, the device enters a saturation region in which the drain current remains relatively constant as the drain-source voltage increases. However, as the drain-source voltage increases still further, impact ionization begins and the drain-to-backgate current begins to increase exponentially. The drain-to-backgate current approximately obeys the equation: EQU I.sub.dbg .perspectiveto.k*10.sup.VDS
Obviously, above a certain drain-source voltage the drain-to-backgate current becomes substantial. Since the drain-to-backgate current varies with the drain-source voltage in a non-linear manner, it appears as a non-linear leakage current to the backgate electrode from the drain of the device. If the device is used as a "gm" gain stage, this leakage current appears as a resistive load on the output which, in turn, produces a non-linear gain.
In order to overcome this problem, prior art circuitry has used shield transistors to reduce the drain-source voltage across an MOS device thereby keeping the drain-source voltage below the level at which impact ionization becomes a significant problem. In particular, it is known to place a common-gate NMOS cascode device in series with an n-channel active device so that the total drain-source voltage is split across the two devices and neither device has a sufficient drain-source voltage across it to cause an impact ionization problem. This prior art approach is discussed in detail in an article entitled "Design Considerations for a High-Performance 3-um CMOS Analog Standard-Cell Library", C. A. Laber, C. F. Rahim, S. F. Dreyer, G. T. Uehara, P. T. Kwok and P. R. Gray, IEEE Journal of Solid-State Circuits, v. SC-22, n. 2, pp 181-189 (April 1987).
Although this prior art approach generally solves the problem of impact ionization, it introduces an additional problem. More particularly, in present prior art shield circuits, the gate voltage of the NMOS shield transistor is fixed, generally at a voltage approximately mid-way between the supply voltages. Consequently, for positive voltage swings of the active device, the shield device goes into saturation, while for negative voltage swings, the shield device enters the deep triode, or linear, region. The abrupt transition between the saturation mode and the linear mode causes the impedance looking into the shield device to go through a step. This transition occurs in all circuits using the prior art circuit and results in an abrupt gain change in the circuit.
Accordingly, it is an object of the present invention to provide a gain correction circuit for an MOS device in which the effects of impact ionization are reduced.
It is another object of the present invention to provide a gain correction circuit for MOS devices in which the effects of impact ionization are reduced while maintaining linear gain in the MOS device.
It is another object of the present invention to provide a gain correction circuit for MOS devices which can be easily integrated into existing device designs.